In today's relatively complex System On Chip (SOC) applications, analog blocks, digital blocks and memories are integrated on the same chip. As SOC devices become more complex, the size of the memories (i.e., number of addresses) increases, with a subsequent increase in chip area to accommodate the memories. Therefore, memories have a significant influence on the overall chip area, and it is desirable to minimize the amount of chip area used by memories to ensure profitability.
Image sensors are manufactured using a pixel cell optimization process. Along with the pixel array, analog blocks, digital blocks and memory are integrated on the same image sensor chip. Currently, the typical memory type used for this application is the standard SRAM (Static Random Access Memory). However, image sensor processes are not optimized for standard SRAM memories, and therefore as the pixel cell continues to shrink, the inability to shrink the SRAM becomes a problem to chip area and profitability.